The present invention relates to integrated circuits and, more particularly, to an integrated circuit having an embedded memory and an integrated electromagnetic shield to allow routing over the embedded memory.
Semiconductor integrated circuits, such as complementary metal-oxide semiconductor (CMOS) circuits are now capable of being fabricated with large amounts of embedded memory. For example, an Application Specific Integrated Circuit (ASIC) which is fabricated with 0.25 micron technology may have an embedded 64 or 128 megabit memory, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).
A difficulty with embedded memory is that signal wires typically cannot be routed over memory. These signal wires can cause capacitive coupling with the signal wires that are routed within the memory. If the capacitive coupling is large enough to change a data value (a one or a zero) of a single memory cell, the data may be corrupted. This is particularly true for DRAM memory since the memory cells have small storage capacitors which are easily corrupted with a small amount of cross coupling.
Several factors aggravate this problem. As the performance of the integrated circuits continues to increase, the frequency of the signals within the integrated circuit increases, which increases the magnitude of the cross coupling. Also, the embedded memory must be compatible with the voltage levels and transistor sizes of the technology in which the integrated circuit is fabricated. As transistor sizes decrease, the voltage levels on the integrated circuit also decrease. This decreases the amount of charge on the small storage capacitors in an embedded DRAM memory. A smaller amount of charge is more easily corrupted. With 0.25 micron technology, the voltage levels on the integrated circuit are usually only 2.5 volts.
A common method of minimizing capacitive coupling is to develop design rules that do not allow signal wires to be routed over embedded memory blocks. The signal wires are routed around the memory rather than over the memory. Unfortunately, this leads to congested routing lanes and sacrifices flexibility in arranging memory and logic blocks, which compromises the density of integrated circuits having embedded memory.